-Description: Add/fix support for m68k, mips, paris, sparc
-Author: Guillem Jover <guillem@debian.org>
-Origin: vendor
-Forwarded: no
-Last-Update: 2014-10-09
-
-
---
- harness/main.c | 10 +++++++++
+ harness/main.c | 10 ++
src/libaio.h | 1
- src/syscall-m68k.h | 5 ++++
- src/syscall-mips.h | 54 +++++++++++++++++++++++++++++++++++++++++++++++++++
- src/syscall-parisc.h | 6 +++++
- src/syscall.h | 6 +++++
- 6 files changed, 82 insertions(+)
+ src/syscall-m68k.h | 78 +++++++++++++++++
+ src/syscall-mips.h | 223 +++++++++++++++++++++++++++++++++++++++++++++++++++
+ src/syscall-parisc.h | 146 +++++++++++++++++++++++++++++++++
+ src/syscall-sparc.h | 20 +++-
+ src/syscall.h | 6 +
+ 7 files changed, 479 insertions(+), 5 deletions(-)
--- /dev/null
+++ b/src/syscall-m68k.h
-@@ -0,0 +1,5 @@
+@@ -0,0 +1,78 @@
+#define __NR_io_setup 241
+#define __NR_io_destroy 242
+#define __NR_io_getevents 243
+#define __NR_io_submit 244
+#define __NR_io_cancel 245
++
++#define io_syscall1(type,fname,sname,atype,a) \
++type fname(atype a) \
++{ \
++register long __res __asm__ ("%d0") = __NR_##sname; \
++register long __a __asm__ ("%d1") = (long)(a); \
++__asm__ __volatile__ ("trap #0" \
++ : "+d" (__res) \
++ : "d" (__a) ); \
++return (type) __res; \
++}
++
++#define io_syscall2(type,fname,sname,atype,a,btype,b) \
++type fname(atype a,btype b) \
++{ \
++register long __res __asm__ ("%d0") = __NR_##sname; \
++register long __a __asm__ ("%d1") = (long)(a); \
++register long __b __asm__ ("%d2") = (long)(b); \
++__asm__ __volatile__ ("trap #0" \
++ : "+d" (__res) \
++ : "d" (__a), "d" (__b) \
++ ); \
++return (type) __res; \
++}
++
++#define io_syscall3(type,fname,sname,atype,a,btype,b,ctype,c) \
++type fname(atype a,btype b,ctype c) \
++{ \
++register long __res __asm__ ("%d0") = __NR_##sname; \
++register long __a __asm__ ("%d1") = (long)(a); \
++register long __b __asm__ ("%d2") = (long)(b); \
++register long __c __asm__ ("%d3") = (long)(c); \
++__asm__ __volatile__ ("trap #0" \
++ : "+d" (__res) \
++ : "d" (__a), "d" (__b), \
++ "d" (__c) \
++ ); \
++return (type) __res; \
++}
++
++#define io_syscall4(type,fname,sname,atype,a,btype,b,ctype,c,dtype,d) \
++type fname (atype a, btype b, ctype c, dtype d) \
++{ \
++register long __res __asm__ ("%d0") = __NR_##sname; \
++register long __a __asm__ ("%d1") = (long)(a); \
++register long __b __asm__ ("%d2") = (long)(b); \
++register long __c __asm__ ("%d3") = (long)(c); \
++register long __d __asm__ ("%d4") = (long)(d); \
++__asm__ __volatile__ ("trap #0" \
++ : "+d" (__res) \
++ : "d" (__a), "d" (__b), \
++ "d" (__c), "d" (__d) \
++ ); \
++return (type) __res; \
++}
++
++#define io_syscall5(type,fname,sname,atype,a,btype,b,ctype,c,dtype,d,etype,e) \
++type fname (atype a,btype b,ctype c,dtype d,etype e) \
++{ \
++register long __res __asm__ ("%d0") = __NR_##sname; \
++register long __a __asm__ ("%d1") = (long)(a); \
++register long __b __asm__ ("%d2") = (long)(b); \
++register long __c __asm__ ("%d3") = (long)(c); \
++register long __d __asm__ ("%d4") = (long)(d); \
++register long __e __asm__ ("%d5") = (long)(e); \
++__asm__ __volatile__ ("trap #0" \
++ : "+d" (__res) \
++ : "d" (__a), "d" (__b), \
++ "d" (__c), "d" (__d), "d" (__e) \
++ ); \
++return (type) __res; \
++}
++
--- a/src/syscall.h
+++ b/src/syscall.h
-@@ -27,6 +27,12 @@
- #include "syscall-arm.h"
- #elif defined(__sparc__)
+@@ -28,6 +28,12 @@
#include "syscall-sparc.h"
+ #elif defined(__aarch64__)
+ #include "syscall-arm64.h"
+#elif defined(__m68k__)
+#include "syscall-m68k.h"
+#elif defined(__hppa__)
+#include "syscall-parisc.h"
+#elif defined(__mips__)
+#include "syscall-mips.h"
- #elif defined(__aarch64__) || defined(__riscv)
- #include "syscall-generic.h"
#else
+ #warning "using generic syscall method"
+ #include "syscall-generic.h"
--- /dev/null
+++ b/src/syscall-mips.h
-@@ -0,0 +1,54 @@
+@@ -0,0 +1,223 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ *
+ * Copyright (C) 1995, 96, 97, 98, 99, 2000 by Ralf Baechle
+ * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
++ *
++ * Changed system calls macros _syscall5 - _syscall7 to push args 5 to 7 onto
++ * the stack. Robin Farine for ACN S.A, Copyright (C) 1996 by ACN S.A
+ */
+
+#ifndef _MIPS_SIM_ABI32
+#define __NR_io_submit (__NR_Linux + 203)
+#define __NR_io_cancel (__NR_Linux + 204)
+#endif /* _MIPS_SIM == _MIPS_SIM_NABI32 */
++
++#define io_syscall1(type,fname,sname,atype,a) \
++type fname(atype a) \
++{ \
++ register unsigned long __a0 asm("$4") = (unsigned long) a; \
++ register unsigned long __a3 asm("$7"); \
++ unsigned long __v0; \
++ \
++ __asm__ volatile ( \
++ ".set\tnoreorder\n\t" \
++ "li\t$2, %3\t\t\t# " #fname "\n\t" \
++ "syscall\n\t" \
++ "move\t%0, $2\n\t" \
++ ".set\treorder" \
++ : "=&r" (__v0), "=r" (__a3) \
++ : "r" (__a0), "i" (__NR_##sname) \
++ : "$2", "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", "$24", \
++ "memory"); \
++ \
++ if (__a3 == 0) \
++ return (type) __v0; \
++ return (type) -1; \
++}
++
++#define io_syscall2(type,fname,sname,atype,a,btype,b) \
++type fname(atype a, btype b) \
++{ \
++ register unsigned long __a0 asm("$4") = (unsigned long) a; \
++ register unsigned long __a1 asm("$5") = (unsigned long) b; \
++ register unsigned long __a3 asm("$7"); \
++ unsigned long __v0; \
++ \
++ __asm__ volatile ( \
++ ".set\tnoreorder\n\t" \
++ "li\t$2, %4\t\t\t# " #fname "\n\t" \
++ "syscall\n\t" \
++ "move\t%0, $2\n\t" \
++ ".set\treorder" \
++ : "=&r" (__v0), "=r" (__a3) \
++ : "r" (__a0), "r" (__a1), "i" (__NR_##sname) \
++ : "$2", "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", "$24", \
++ "memory"); \
++ \
++ if (__a3 == 0) \
++ return (type) __v0; \
++ return (type) -1; \
++}
++
++#define io_syscall3(type,fname,sname,atype,a,btype,b,ctype,c) \
++type fname(atype a, btype b, ctype c) \
++{ \
++ register unsigned long __a0 asm("$4") = (unsigned long) a; \
++ register unsigned long __a1 asm("$5") = (unsigned long) b; \
++ register unsigned long __a2 asm("$6") = (unsigned long) c; \
++ register unsigned long __a3 asm("$7"); \
++ unsigned long __v0; \
++ \
++ __asm__ volatile ( \
++ ".set\tnoreorder\n\t" \
++ "li\t$2, %5\t\t\t# " #fname "\n\t" \
++ "syscall\n\t" \
++ "move\t%0, $2\n\t" \
++ ".set\treorder" \
++ : "=&r" (__v0), "=r" (__a3) \
++ : "r" (__a0), "r" (__a1), "r" (__a2), "i" (__NR_##sname) \
++ : "$2", "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", "$24", \
++ "memory"); \
++ \
++ if (__a3 == 0) \
++ return (type) __v0; \
++ return (type) -1; \
++}
++
++#define io_syscall4(type,fname,sname,atype,a,btype,b,ctype,c,dtype,d) \
++type fname(atype a, btype b, ctype c, dtype d) \
++{ \
++ register unsigned long __a0 asm("$4") = (unsigned long) a; \
++ register unsigned long __a1 asm("$5") = (unsigned long) b; \
++ register unsigned long __a2 asm("$6") = (unsigned long) c; \
++ register unsigned long __a3 asm("$7") = (unsigned long) d; \
++ unsigned long __v0; \
++ \
++ __asm__ volatile ( \
++ ".set\tnoreorder\n\t" \
++ "li\t$2, %5\t\t\t# " #fname "\n\t" \
++ "syscall\n\t" \
++ "move\t%0, $2\n\t" \
++ ".set\treorder" \
++ : "=&r" (__v0), "+r" (__a3) \
++ : "r" (__a0), "r" (__a1), "r" (__a2), "i" (__NR_##sname) \
++ : "$2", "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", "$24", \
++ "memory"); \
++ \
++ if (__a3 == 0) \
++ return (type) __v0; \
++ return (type) -1; \
++}
++
++#if (_MIPS_SIM == _MIPS_SIM_ABI32)
++
++/*
++ * Using those means your brain needs more than an oil change ;-)
++ */
++
++#define io_syscall5(type,fname,sname,atype,a,btype,b,ctype,c,dtype,d,etype,e) \
++type fname(atype a, btype b, ctype c, dtype d, etype e) \
++{ \
++ register unsigned long __a0 asm("$4") = (unsigned long) a; \
++ register unsigned long __a1 asm("$5") = (unsigned long) b; \
++ register unsigned long __a2 asm("$6") = (unsigned long) c; \
++ register unsigned long __a3 asm("$7") = (unsigned long) d; \
++ unsigned long __v0; \
++ \
++ __asm__ volatile ( \
++ ".set\tnoreorder\n\t" \
++ "lw\t$2, %6\n\t" \
++ "subu\t$29, 32\n\t" \
++ "sw\t$2, 16($29)\n\t" \
++ "li\t$2, %5\t\t\t# " #fname "\n\t" \
++ "syscall\n\t" \
++ "move\t%0, $2\n\t" \
++ "addiu\t$29, 32\n\t" \
++ ".set\treorder" \
++ : "=&r" (__v0), "+r" (__a3) \
++ : "r" (__a0), "r" (__a1), "r" (__a2), "i" (__NR_##sname), \
++ "m" ((unsigned long)e) \
++ : "$2", "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", "$24", \
++ "memory"); \
++ \
++ if (__a3 == 0) \
++ return (type) __v0; \
++ return (type) -1; \
++}
++
++#endif /* (_MIPS_SIM == _MIPS_SIM_ABI32) */
++
++#if (_MIPS_SIM == _MIPS_SIM_NABI32) || (_MIPS_SIM == _MIPS_SIM_ABI64)
++
++#define io_syscall5(type,fname,sname,atype,a,btype,b,ctype,c,dtype,d,etype,e) \
++type fname (atype a,btype b,ctype c,dtype d,etype e) \
++{ \
++ register unsigned long __a0 asm("$4") = (unsigned long) a; \
++ register unsigned long __a1 asm("$5") = (unsigned long) b; \
++ register unsigned long __a2 asm("$6") = (unsigned long) c; \
++ register unsigned long __a3 asm("$7") = (unsigned long) d; \
++ register unsigned long __a4 asm("$8") = (unsigned long) e; \
++ unsigned long __v0; \
++ \
++ __asm__ volatile ( \
++ ".set\tnoreorder\n\t" \
++ "li\t$2, %6\t\t\t# " #fname "\n\t" \
++ "syscall\n\t" \
++ "move\t%0, $2\n\t" \
++ ".set\treorder" \
++ : "=&r" (__v0), "+r" (__a3) \
++ : "r" (__a0), "r" (__a1), "r" (__a2), "r" (__a4), "i" (__NR_##sname) \
++ : "$2", "$9", "$10", "$11", "$12", "$13", "$14", "$15", "$24", \
++ "memory"); \
++ \
++ if (__a3 == 0) \
++ return (type) __v0; \
++ return (type) -1; \
++}
++
++#endif /* (_MIPS_SIM == _MIPS_SIM_NABI32) || (_MIPS_SIM == _MIPS_SIM_ABI64) */
++
--- a/src/libaio.h
+++ b/src/libaio.h
-@@ -71,6 +71,7 @@ typedef enum io_iocb_cmd {
+@@ -66,6 +66,7 @@ typedef enum io_iocb_cmd {
/* big endian, 64 bits */
#elif defined(__powerpc64__) || defined(__s390x__) || \
+ (defined(__hppa__) && defined(__arch64__)) || \
(defined(__sparc__) && defined(__arch64__)) || \
- (defined(__aarch64__) && defined(__AARCH64EB__)) || \
- (defined(__GNUC__) && defined(__BYTE_ORDER__) && \
+ (defined(__aarch64__) && defined(__AARCH64EB__))
+ #define PADDED(x, y) unsigned y; x
--- /dev/null
+++ b/src/syscall-parisc.h
-@@ -0,0 +1,6 @@
+@@ -0,0 +1,146 @@
++/*
++ * Linux system call numbers.
++ *
++ * Cary Coutant says that we should just use another syscall gateway
++ * page to avoid clashing with the HPUX space, and I think he's right:
++ * it will would keep a branch out of our syscall entry path, at the
++ * very least. If we decide to change it later, we can ``just'' tweak
++ * the LINUX_GATEWAY_ADDR define at the bottom and make __NR_Linux be
++ * 1024 or something. Oh, and recompile libc. =)
++ *
++ * 64-bit HPUX binaries get the syscall gateway address passed in a register
++ * from the kernel at startup, which seems a sane strategy.
++ */
++
+#define __NR_Linux 0
+#define __NR_io_setup (__NR_Linux + 215)
+#define __NR_io_destroy (__NR_Linux + 216)
+#define __NR_io_getevents (__NR_Linux + 217)
+#define __NR_io_submit (__NR_Linux + 218)
+#define __NR_io_cancel (__NR_Linux + 219)
++
++#define SYS_ify(syscall_name) __NR_##syscall_name
++
++/* Assume all syscalls are done from PIC code just to be
++ * safe. The worst case scenario is that you lose a register
++ * and save/restore r19 across the syscall. */
++#define PIC
++
++/* Definition taken from glibc 2.3.3
++ * sysdeps/unix/sysv/linux/hppa/sysdep.h
++ */
++
++#ifdef PIC
++/* WARNING: CANNOT BE USED IN A NOP! */
++# define K_STW_ASM_PIC " copy %%r19, %%r4\n"
++# define K_LDW_ASM_PIC " copy %%r4, %%r19\n"
++# define K_USING_GR4 "%r4",
++#else
++# define K_STW_ASM_PIC " \n"
++# define K_LDW_ASM_PIC " \n"
++# define K_USING_GR4
++#endif
++
++/* GCC has to be warned that a syscall may clobber all the ABI
++ registers listed as "caller-saves", see page 8, Table 2
++ in section 2.2.6 of the PA-RISC RUN-TIME architecture
++ document. However! r28 is the result and will conflict with
++ the clobber list so it is left out. Also the input arguments
++ registers r20 -> r26 will conflict with the list so they
++ are treated specially. Although r19 is clobbered by the syscall
++ we cannot say this because it would violate ABI, thus we say
++ r4 is clobbered and use that register to save/restore r19
++ across the syscall. */
++
++#define K_CALL_CLOB_REGS "%r1", "%r2", K_USING_GR4 \
++ "%r20", "%r29", "%r31"
++
++#undef K_INLINE_SYSCALL
++#define K_INLINE_SYSCALL(name, nr, args...) ({ \
++ long __sys_res; \
++ { \
++ register unsigned long __res __asm__("r28"); \
++ K_LOAD_ARGS_##nr(args) \
++ /* FIXME: HACK stw/ldw r19 around syscall */ \
++ __asm__ volatile( \
++ K_STW_ASM_PIC \
++ " ble 0x100(%%sr2, %%r0)\n" \
++ " ldi %1, %%r20\n" \
++ K_LDW_ASM_PIC \
++ : "=r" (__res) \
++ : "i" (SYS_ify(name)) K_ASM_ARGS_##nr \
++ : "memory", K_CALL_CLOB_REGS K_CLOB_ARGS_##nr \
++ ); \
++ __sys_res = (long)__res; \
++ } \
++ __sys_res; \
++})
++
++#define K_LOAD_ARGS_0()
++#define K_LOAD_ARGS_1(r26) \
++ register unsigned long __r26 __asm__("r26") = (unsigned long)(r26); \
++ K_LOAD_ARGS_0()
++#define K_LOAD_ARGS_2(r26,r25) \
++ register unsigned long __r25 __asm__("r25") = (unsigned long)(r25); \
++ K_LOAD_ARGS_1(r26)
++#define K_LOAD_ARGS_3(r26,r25,r24) \
++ register unsigned long __r24 __asm__("r24") = (unsigned long)(r24); \
++ K_LOAD_ARGS_2(r26,r25)
++#define K_LOAD_ARGS_4(r26,r25,r24,r23) \
++ register unsigned long __r23 __asm__("r23") = (unsigned long)(r23); \
++ K_LOAD_ARGS_3(r26,r25,r24)
++#define K_LOAD_ARGS_5(r26,r25,r24,r23,r22) \
++ register unsigned long __r22 __asm__("r22") = (unsigned long)(r22); \
++ K_LOAD_ARGS_4(r26,r25,r24,r23)
++#define K_LOAD_ARGS_6(r26,r25,r24,r23,r22,r21) \
++ register unsigned long __r21 __asm__("r21") = (unsigned long)(r21); \
++ K_LOAD_ARGS_5(r26,r25,r24,r23,r22)
++
++/* Even with zero args we use r20 for the syscall number */
++#define K_ASM_ARGS_0
++#define K_ASM_ARGS_1 K_ASM_ARGS_0, "r" (__r26)
++#define K_ASM_ARGS_2 K_ASM_ARGS_1, "r" (__r25)
++#define K_ASM_ARGS_3 K_ASM_ARGS_2, "r" (__r24)
++#define K_ASM_ARGS_4 K_ASM_ARGS_3, "r" (__r23)
++#define K_ASM_ARGS_5 K_ASM_ARGS_4, "r" (__r22)
++#define K_ASM_ARGS_6 K_ASM_ARGS_5, "r" (__r21)
++
++/* The registers not listed as inputs but clobbered */
++#define K_CLOB_ARGS_6
++#define K_CLOB_ARGS_5 K_CLOB_ARGS_6, "%r21"
++#define K_CLOB_ARGS_4 K_CLOB_ARGS_5, "%r22"
++#define K_CLOB_ARGS_3 K_CLOB_ARGS_4, "%r23"
++#define K_CLOB_ARGS_2 K_CLOB_ARGS_3, "%r24"
++#define K_CLOB_ARGS_1 K_CLOB_ARGS_2, "%r25"
++#define K_CLOB_ARGS_0 K_CLOB_ARGS_1, "%r26"
++
++#define io_syscall1(type,fname,sname,type1,arg1) \
++type fname(type1 arg1) \
++{ \
++ return K_INLINE_SYSCALL(sname, 1, arg1); \
++}
++
++#define io_syscall2(type,fname,sname,type1,arg1,type2,arg2) \
++type fname(type1 arg1, type2 arg2) \
++{ \
++ return K_INLINE_SYSCALL(sname, 2, arg1, arg2); \
++}
++
++#define io_syscall3(type,fname,sname,type1,arg1,type2,arg2,type3,arg3) \
++type fname(type1 arg1, type2 arg2, type3 arg3) \
++{ \
++ return K_INLINE_SYSCALL(sname, 3, arg1, arg2, arg3); \
++}
++
++#define io_syscall4(type,fname,sname,type1,arg1,type2,arg2,type3,arg3,type4,arg4) \
++type fname(type1 arg1, type2 arg2, type3 arg3, type4 arg4) \
++{ \
++ return K_INLINE_SYSCALL(sname, 4, arg1, arg2, arg3, arg4); \
++}
++
++#define io_syscall5(type,fname,sname,type1,arg1,type2,arg2,type3,arg3,type4,arg4,type5,arg5) \
++type fname(type1 arg1, type2 arg2, type3 arg3, type4 arg4, type5 arg5) \
++{ \
++ return K_INLINE_SYSCALL(sname, 5, arg1, arg2, arg3, arg4, arg5); \
++}
++
--- a/harness/main.c
+++ b/harness/main.c
@@ -12,7 +12,17 @@
#else
//#warning Not really sure where kernel memory is. Guessing.
#define KERNEL_RW_POINTER ((void *)0xffffffff81000000)
+--- a/src/syscall-sparc.h
++++ b/src/syscall-sparc.h
+@@ -20,7 +20,9 @@ __asm__ __volatile__ ("t 0x10\n\t" \
+ : "=r" (__res), "=&r" (__o0) \
+ : "1" (__o0), "r" (__g1) \
+ : "cc"); \
+-return (type) __res; \
++if (__res < -255 || __res >= 0) \
++ return (type) __res; \
++return -1; \
+ }
+
+ #define io_syscall2(type,fname,sname,type1,arg1,type2,arg2) \
+@@ -38,7 +40,9 @@ __asm__ __volatile__ ("t 0x10\n\t" \
+ : "=r" (__res), "=&r" (__o0) \
+ : "1" (__o0), "r" (__o1), "r" (__g1) \
+ : "cc"); \
+-return (type) __res; \
++if (__res < -255 || __res >= 0) \
++ return (type) __res; \
++return -1; \
+ }
+
+ #define io_syscall3(type,fname,sname,type1,arg1,type2,arg2,type3,arg3) \
+@@ -57,7 +61,9 @@ __asm__ __volatile__ ("t 0x10\n\t" \
+ : "=r" (__res), "=&r" (__o0) \
+ : "1" (__o0), "r" (__o1), "r" (__o2), "r" (__g1) \
+ : "cc"); \
+-return (type) __res; \
++if (__res < -255 || __res >= 0) \
++ return (type) __res; \
++return -1; \
+ }
+
+ #define io_syscall4(type,fname,sname,type1,arg1,type2,arg2,type3,arg3,type4,arg4) \
+@@ -77,7 +83,9 @@ __asm__ __volatile__ ("t 0x10\n\t" \
+ : "=r" (__res), "=&r" (__o0) \
+ : "1" (__o0), "r" (__o1), "r" (__o2), "r" (__o3), "r" (__g1) \
+ : "cc"); \
+-return (type) __res; \
++if (__res < -255 || __res >= 0) \
++ return (type) __res; \
++return -1; \
+ }
+
+ #define io_syscall5(type,fname,sname,type1,arg1,type2,arg2,type3,arg3,type4,arg4, \
+@@ -99,5 +107,7 @@ __asm__ __volatile__ ("t 0x10\n\t" \
+ : "=r" (__res), "=&r" (__o0) \
+ : "1" (__o0), "r" (__o1), "r" (__o2), "r" (__o3), "r" (__o4), "r" (__g1) \
+ : "cc"); \
+-return (type) __res; \
++if (__res < -255 || __res >= 0) \
++ return (type) __res; \
++return -1; \
+ }
-Author: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
-Description: Add SH supprt
- The test-suite logs can be found at:
- .
- <https://bugs.debian.org/cgi-bin/bugreport.cgi?bug=535288>
+From: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+Subject: Add SH supprt
+
+The test-suite logs can be found at:
+
+ <http://bugs.debian.org/cgi-bin/bugreport.cgi?bug=535288>
---
- harness/main.c | 2 +-
- src/libaio.h | 4 +++-
- src/syscall-sh.h | 6 ++++++
- src/syscall.h | 2 ++
- 4 files changed, 12 insertions(+), 2 deletions(-)
+ harness/main.c | 2 -
+ src/libaio.h | 4 ++
+ src/syscall-sh.h | 78 +++++++++++++++++++++++++++++++++++++++++++++++++++++++
+ src/syscall.h | 2 +
+ 4 files changed, 84 insertions(+), 2 deletions(-)
--- a/harness/main.c
- defined(__sh__) || defined(__bfin__) || defined(__MIPSEL__) || \
+ (defined(__sh__) && defined(__LITTLE_ENDIAN__)) || \
+ defined(__bfin__) || defined(__MIPSEL__) || \
- defined(__cris__) || (defined(__riscv) && __riscv_xlen == 32) || \
- (defined(__GNUC__) && defined(__BYTE_ORDER__) && \
- __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__ && __SIZEOF_LONG__ == 4)
-@@ -83,6 +84,7 @@ typedef enum io_iocb_cmd {
+ defined(__cris__)
+ #define PADDED(x, y) x; unsigned y
+ #define PADDEDptr(x, y) x; unsigned y
+@@ -76,6 +77,7 @@ typedef enum io_iocb_cmd {
/* big endian, 32 bits */
#elif defined(__PPC__) || defined(__s390__) || \
(defined(__arm__) && defined(__ARMEB__)) || \
+ (defined(__sh__) && defined (__BIG_ENDIAN__)) || \
defined(__sparc__) || defined(__MIPSEB__) || defined(__m68k__) || \
- defined(__hppa__) || defined(__frv__) || defined(__avr32__) || \
- (defined(__GNUC__) && defined(__BYTE_ORDER__) && \
+ defined(__hppa__) || defined(__frv__) || defined(__avr32__)
+ #define PADDED(x, y) unsigned y; x
--- /dev/null
+++ b/src/syscall-sh.h
-@@ -0,0 +1,6 @@
+@@ -0,0 +1,78 @@
+/* Copy from ./arch/sh/include/asm/unistd_32.h */
+#define __NR_io_setup 245
+#define __NR_io_destroy 246
+#define __NR_io_getevents 247
+#define __NR_io_submit 248
+#define __NR_io_cancel 249
++
++#define io_syscall1(type,fname,sname,type1,arg1) \
++type fname(type1 arg1) \
++{ \
++register long __sc0 __asm__ ("r3") = __NR_##sname; \
++register long __sc4 __asm__ ("r4") = (long) arg1; \
++__asm__ __volatile__ ("trapa #0x11" \
++ : "=z" (__sc0) \
++ : "0" (__sc0), "r" (__sc4) \
++ : "memory"); \
++ return (type) __sc0;\
++}
++
++#define io_syscall2(type,fname,sname,type1,arg1,type2,arg2) \
++type fname(type1 arg1,type2 arg2) \
++{ \
++register long __sc0 __asm__ ("r3") = __NR_##sname; \
++register long __sc4 __asm__ ("r4") = (long) arg1; \
++register long __sc5 __asm__ ("r5") = (long) arg2; \
++ __asm__ __volatile__ ("trapa #0x12" \
++ : "=z" (__sc0) \
++ : "0" (__sc0), "r" (__sc4), "r" (__sc5) \
++ : "memory"); \
++ return (type) __sc0;\
++}
++
++#define io_syscall3(type,fname,sname,type1,arg1,type2,arg2,type3,arg3) \
++type fname(type1 arg1,type2 arg2,type3 arg3) \
++{ \
++register long __sc0 __asm__ ("r3") = __NR_##sname; \
++register long __sc4 __asm__ ("r4") = (long) arg1; \
++register long __sc5 __asm__ ("r5") = (long) arg2; \
++register long __sc6 __asm__ ("r6") = (long) arg3; \
++ __asm__ __volatile__ ("trapa #0x13" \
++ : "=z" (__sc0) \
++ : "0" (__sc0), "r" (__sc4), "r" (__sc5), "r" (__sc6) \
++ : "memory"); \
++ return (type) __sc0;\
++}
++
++#define io_syscall4(type,fname,sname,type1,arg1,type2,arg2,type3,arg3,type4,arg4) \
++type fname(type1 arg1, type2 arg2, type3 arg3, type4 arg4) \
++{ \
++register long __sc0 __asm__ ("r3") = __NR_##sname; \
++register long __sc4 __asm__ ("r4") = (long) arg1; \
++register long __sc5 __asm__ ("r5") = (long) arg2; \
++register long __sc6 __asm__ ("r6") = (long) arg3; \
++register long __sc7 __asm__ ("r7") = (long) arg4; \
++__asm__ __volatile__ ("trapa #0x14" \
++ : "=z" (__sc0) \
++ : "0" (__sc0), "r" (__sc4), "r" (__sc5), "r" (__sc6), \
++ "r" (__sc7) \
++ : "memory" ); \
++ return (type) __sc0;\
++}
++
++#define io_syscall5(type,fname,sname,type1,arg1,type2,arg2,type3,arg3,type4,arg4,type5,arg5) \
++type fname(type1 arg1, type2 arg2, type3 arg3, type4 arg4, type5 arg5) \
++{ \
++register long __sc3 __asm__ ("r3") = __NR_##sname; \
++register long __sc4 __asm__ ("r4") = (long) arg1; \
++register long __sc5 __asm__ ("r5") = (long) arg2; \
++register long __sc6 __asm__ ("r6") = (long) arg3; \
++register long __sc7 __asm__ ("r7") = (long) arg4; \
++register long __sc0 __asm__ ("r0") = (long) arg5; \
++__asm__ __volatile__ ("trapa #0x15" \
++ : "=z" (__sc0) \
++ : "0" (__sc0), "r" (__sc4), "r" (__sc5), "r" (__sc6), "r" (__sc7), \
++ "r" (__sc3) \
++ : "memory" ); \
++ return (type) __sc0;\
++}
--- a/src/syscall.h
+++ b/src/syscall.h
-@@ -33,6 +33,8 @@
+@@ -34,6 +34,8 @@
#include "syscall-parisc.h"
#elif defined(__mips__)
#include "syscall-mips.h"
+#elif defined(__sh__)
+#include "syscall-sh.h"
- #elif defined(__aarch64__) || defined(__riscv)
- #include "syscall-generic.h"
#else
+ #warning "using generic syscall method"
+ #include "syscall-generic.h"
--- /dev/null
+---
+ src/syscall-sparc64.h | 98 ++++++++++++++++++++++++++++++++++++++++++++++++++
+ src/syscall.h | 2 +
+ 2 files changed, 100 insertions(+)
+
+--- a/src/syscall.h
++++ b/src/syscall.h
+@@ -24,6 +24,8 @@
+ #include "syscall-alpha.h"
+ #elif defined(__arm__)
+ #include "syscall-arm.h"
++#elif defined(__sparc__) && defined(__arch64__)
++#include "syscall-sparc64.h"
+ #elif defined(__sparc__)
+ #include "syscall-sparc.h"
+ #elif defined(__aarch64__)
+--- /dev/null
++++ b/src/syscall-sparc64.h
+@@ -0,0 +1,98 @@
++#define __NR_io_setup 268
++#define __NR_io_destroy 269
++#define __NR_io_submit 270
++#define __NR_io_cancel 271
++#define __NR_io_getevents 272
++
++#define io_syscall1(type,fname,sname,type1,arg1) \
++type fname(type1 arg1) \
++{ \
++ unsigned long __res; \
++ register unsigned long __g1 __asm__("g1") = __NR_##sname; \
++ register unsigned long __o0 __asm__("o0") = (unsigned long) arg1; \
++ __asm__ __volatile__("t 0x6d\n\t" \
++ "sub %%g0, %%o0, %0\n\t" \
++ "movcc %%xcc, %%o0, %0\n" \
++ "1:" \
++ : "=r" (__res), "=&r" (__o0) \
++ : "1" (__o0), "r" (__g1) \
++ : "cc"); \
++ return (type) __res; \
++}
++
++#define io_syscall2(type,fname,sname,type1,arg1,type2,arg2) \
++type fname(type1 arg1, type2 arg2) \
++{ \
++ unsigned long __res; \
++ register unsigned long __g1 __asm__("g1") = __NR_##sname; \
++ register unsigned long __o0 __asm__("o0") = (unsigned long) arg1; \
++ register unsigned long __o1 __asm__("o1") = (unsigned long) arg2; \
++ __asm__ __volatile__("t 0x6d\n\t" \
++ "sub %%g0, %%o0, %0\n\t" \
++ "movcc %%xcc, %%o0, %0\n" \
++ "1:" \
++ : "=r" (__res), "=&r" (__o0) \
++ : "1" (__o0), "r" (__o1), "r" (__g1) \
++ : "cc"); \
++ return (type) __res; \
++}
++
++#define io_syscall3(type,fname,sname,type1,arg1,type2,arg2,type3,arg3) \
++type fname(type1 arg1, type2 arg2, type3 arg3) \
++{ \
++ unsigned long __res; \
++ register unsigned long __g1 __asm__("g1") = __NR_##sname; \
++ register unsigned long __o0 __asm__("o0") = (unsigned long) arg1; \
++ register unsigned long __o1 __asm__("o1") = (unsigned long) arg2; \
++ register unsigned long __o2 __asm__("o2") = (unsigned long) arg3; \
++ __asm__ __volatile__("t 0x6d\n\t" \
++ "sub %%g0, %%o0, %0\n\t" \
++ "movcc %%xcc, %%o0, %0\n" \
++ "1:" \
++ : "=r" (__res), "=&r" (__o0) \
++ : "1" (__o0), "r" (__o1), "r" (__o2), \
++ "r" (__g1) \
++ : "cc"); \
++ return (type) __res; \
++}
++
++#define io_syscall4(type,fname,sname,type1,arg1,type2,arg2,type3,arg3,type4,arg4) \
++type fname(type1 arg1, type2 arg2, type3 arg3, type4 arg4) \
++{ \
++ unsigned long __res; \
++ register unsigned long __g1 __asm__("g1") = __NR_##sname; \
++ register unsigned long __o0 __asm__("o0") = (unsigned long) arg1; \
++ register unsigned long __o1 __asm__("o1") = (unsigned long) arg2; \
++ register unsigned long __o2 __asm__("o2") = (unsigned long) arg3; \
++ register unsigned long __o3 __asm__("o3") = (unsigned long) arg4; \
++ __asm__ __volatile__("t 0x6d\n\t" \
++ "sub %%g0, %%o0, %0\n\t" \
++ "movcc %%xcc, %%o0, %0\n" \
++ "1:" \
++ : "=r" (__res), "=&r" (__o0) \
++ : "1" (__o0), "r" (__o1), "r" (__o2), \
++ "r" (__o3), "r" (__g1) \
++ : "cc"); \
++ return (type) __res; \
++}
++
++#define io_syscall5(type,fname,sname,type1,arg1,type2,arg2,type3,arg3,type4,arg4,type5,arg5) \
++type fname(type1 arg1, type2 arg2, type3 arg3, type4 arg4, type5 arg5) \
++{ \
++ unsigned long __res; \
++ register unsigned long __g1 __asm__("g1") = __NR_##sname; \
++ register unsigned long __o0 __asm__("o0") = (unsigned long) arg1; \
++ register unsigned long __o1 __asm__("o1") = (unsigned long) arg2; \
++ register unsigned long __o2 __asm__("o2") = (unsigned long) arg3; \
++ register unsigned long __o3 __asm__("o3") = (unsigned long) arg4; \
++ register unsigned long __o4 __asm__("o4") = (unsigned long) arg5; \
++ __asm__ __volatile__("t 0x6d\n\t" \
++ "sub %%g0, %%o0, %0\n\t" \
++ "movcc %%xcc, %%o0, %0\n" \
++ "1:" \
++ : "=r" (__res), "=&r" (__o0) \
++ : "1" (__o0), "r" (__o1), "r" (__o2), \
++ "r" (__o3), "r" (__o4), "r" (__g1) \
++ : "cc"); \
++ return (type) __res; \
++}
git.99rst.org / openwrt-packages.git / commitdiff